1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device including an auto-precharge function for automatically resetting a word line and of precharging a bit line after ending a read operation or a write operation.
2. Description of Related Art
An operation performed by a synchronous DRAM (Dynamic Random Access Memory), which is a representative semiconductor memory device, is controlled based on a command and an address issued synchronously with an external clock signal. Specifically, when a row address is supplied to a synchronous DRAM synchronously with an active command and then a column address is supplied thereto synchronously with a read command, read data is output from the DRAM after passage of CAS latency since an input of the read command. Furthermore, when a row address is supplied to the DRAM synchronously with an active command and then a column address is supplied thereto synchronously with a write command, write data can be input to the DRAM after passage of CAS write latency since an input of the write command.
After performing such a read operation or a write operation, the DRAM issues a precharge command, thereby resetting a word line and precharging a bit line.
In recent years, synchronous DRAMs often include “auto-precharge function” for automatically resetting word lines and of precharging bit lines after performing a read operation or a write operation (see Japanese Patent Application Laid-open No. H11-306760). A DRAM of this type can designate whether to perform auto-precharge at the time a read command or a write command being issued by using a predetermined address pin. Accordingly, there is no need to input a precharge command to the DRAM after ending the operation, and it suffices to only designate the auto-precharge at the time of issuing the read command or the write command.
Meanwhile, some users wish to input a precharge command without using any auto-precharge function. In such a case, it is not required to designate auto-precharge at the time of issuing a read command or a write command.
When a DRAM is to perform auto-precharge using an auto-precharge function, it is necessary to execute precharge after data is correctly written (or re-written during a read operation) to each memory cell, that is, after passage of a sufficient write recovery period. Due to this necessity, it is required for the DRAM to include a counter circuit that measures the write recovery period so as to realize the auto-precharge function.
However, conventional synchronous DRAMs have the following problems. Because clocks used for recent synchronous DRAMs have quite high frequency, it is necessary to provide multistage flip-flop circuits in the counter circuit used to count the write recovery period. Even if the auto-precharge function is not operated, the counter circuit performs a counting operation whenever a read operation or a write operation is performed. As a result, the DRAM consumes large power when the auto-precharge function is not operated.
There has been strong demand for lower power consumption in synchronous DRAMs and it has been desired to reduce the unnecessary power consumption as described above.